With rapid digital transformation and increasing adoption of AI-enabled IoT solutions across industries, the need for high performance processors and chipsets is also rising. However, chipmakers are finding it difficult to integrate more transistors in a fixed area of a silicon die to achieve marginal improvements in chip performance. Thus, alternatives are being explored, and chiplets are one viable option. This blog provides an overview of what chiplets are and their benefits.
For deeper insights into the subject, Transforma Insights has recently published a report on Chiplets titled, ‘Chiplets are a viable chipset solution for a variety of AIoT applications’, providing insights into chiplet market dynamics, as well as the benefits and challenges related to the development and adoption.
Chiplets are modular and discrete semiconductor components that are designed and developed individually, with specific functions, and combined with other chiplets to form a larger, more complex, system-on-chip (SoC). Unlike monolithic systems-on-chips, which have all the functional units such as compute, I/O, memory, and storage assembled onto a single die, chiplets disaggregate the functional units into multiple specialised dies and the resulting chiplets are subsequently integrated together into a single package.
Integrated chip designers are finding it difficult to achieve higher performance by adding more transistors into a fixed area of a silicon die, as the reticle size (the size of a photomask that can be processed with a single exposure in lithography) is ~860 square millimetres. This is one of the prominent limitations faced by chip designers, which results in the exploration of a multi-chiplet architecture with the main objective to design SoC components (chiplets) for a dedicated function and connecting them through an advanced integration technology for the efficient performance of a combined SoC.
Chiplets offer various benefits to chipmakers to overcome the performance barriers often encountered while developing monolithic system-on-chips. With a multi-die chip architecture, chiplets can be produced on a smaller area and therefore the probability of defects also decreases resulting in better yield.
Furthermore, chip designers can leverage different processing nodes suitable for a particular chipset function, which not only allows chipmakers to reuse existing chiplet IP but also expedites the chiplet development process and thus can also reduce the development costs of multi-die SoCs. Also, the modular architecture of chiplets allows chip designers to customise SoCs based on the requirements of the end-application and use-case.
Chiplet-based architecture has been used in PCs and tablets and shows potential in smart wearables. The modular architecture enables businesses to pack the necessary functional units in a limited space to power these devices. They can balance the cost, compute and energy requirements by using less advanced processing nodes for less critical and non-computing purposes, while using advanced processing nodes for compute.
Similarly, the automotive industry is looking to unlock benefits by using chiplets to cater for increasing demand for high compute requirements to power various applications in software-driven vehicles, such as in-vehicle infotainment and navigation systems. The modular architecture of chiplets enables OEMs to relatively easily change computing or other functionalities of a chiplet system, reducing the need to design a dedicated chip for a particular function, and instead use plug-and-play chiplets.
Industry collaborations are taking place to develop reference chiplet designs that can be reused. This not only eliminates vendor lock-in issues but can expedite the chiplet development process. For instance, late last year, Cadence announced the first Arm Chiplet System Architecture (CSA)-based system SoC integrating processors, memory, and system IP in a package interconnected via UCIe.
Concluding remarks
The true benefits of a chiplet-based architecture can only be realised when a marketplace has emerged where multiple vendors can actively participate. Such an ecosystem must focus on delivering interoperable chiplets that consistently meet the desired parameters and standards, such as thermal characteristics, design and space layout, and electrical properties. When these factors are streamlined and widely adopted, SoC designers will be able to seamlessly combine chiplets from different suppliers. This will unlock the ability to build highly optimised chiplet-based systems, which can achieve the desired balance of power, performance, and cost parameters across a range of applications.
